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    Sr Digital Engineer - Koto City, 日本 - Renesas Electronics

    Renesas Electronics
    Renesas Electronics Koto City, 日本

    1週間前

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    フルタイム
    説明
    Job Description

    Interpreting requirements specifications to develop digital designs from the block level to top-level system for Dialog's mixed-signal IC products.

    Design verification and developing advanced verification methodologies. RTL Design for low power products. Contribution to innovation of designs approaches and methodologies.


    • Design of optimized digital blocks meeting functional, cost and low power constraints and ensure spec compliance.
    • Take over technical leadership for subsystems or for complete digital system and drive from specification to production ramp.
    • Develop TCL scripts and design constraints to perform synthesis, DFT insertion and static timing analysis.
    • Support DFT strategy and implementation.
    • Verification planning, feature extraction and verification test case development.
    • Interface with P & R for Digital handoff and post layout verification.
    • Develop test vectors for production test.
    • Instigate review meetings with Design Engineers.
    • Perform physical silicon device evaluation where necessary.
    • Develop workaround solutions where necessary to overcome device errata including documentation.
    • Support RFQ process where necessary.
    • Coach and mentor less experienced team members.
    Qualifications

    【Must】
    ・Degree level qualification in Electronics Engineering or a related discipline typically required

    ・English:
    Business Level

    【Want】
    ・Typically 5 – 8 years experience
    ・Experience working in semiconductors ideally PMIC or Audio with focus on mixed signal integrated circuits and low power digital design techniques
    Fluent in either (System) Verilog or VHDL RTL coding and ASIC design methodology
    ・Proven ability to optimize and develop design architecture from chip inception to compliant netlist
    ​​​​​​​・Proficiency in developing block and top level timing constraints for STA and P & R sign off
    ​​​​​​​・Experience of scan insertion and ATPG generation
    ​​​​​​​・Technical expert of industry standard tools and procedures
    ​​​​​​​・Ability to work with minimal instruction – either independently or collaboratively
    ​​​​​​​・Ability to make good judgement in selecting method/technique for obtaining solutions
    ​​​​​​​・Able to confidently share own expertise and work to colleagues and customers
    ​​​​​​​・Able to make significant contribution to projects, programs and business initiatives through creativity and ingenuity
    ​​​​​​​・Results-oriented and able to deliver on-time under a tight schedule
    ​​​​​​​・Ability to work both independently and part of a team
    ​​​​​​​・Flexible to undertake occasional international travel at short notice
    ​​​​​​​・Ability to propose innovative solutions

    ・Japanese:
    Business Level


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